--! Cascade of half band filters with decimation
entity HbfCascade is
	port (
		Clk        	: in  std_logic; --! System clock (assumed 100 MHz)
		Init       	: in  std_logic; --! Synchronous reset
		AdcIn 		: in  std_logic_vector(15 downto 0); --! ADC Signal from periphery
		AdcValid  	: in  std_logic; --! New Sample of ADC is available
		FilterOut 	: out std_logic_vector(21 downto 0); --! Filtered output
		FilterValid	: out  std_logic --! New Sample of Filter Data is available
	);
end HbfCascade;

-- interface from controller to signal stage process completed
signal StageR       : integer range 0 to 7;          -- Stufenauswahl
signal StageReadR   : std_logic;                     -- Leseerlaubnis

-- Zeiger und Füllstand
signal Stage1WrPtr  : unsigned(4 downto 0);          -- 5-Bit Schreibzeiger
signal ResStage1WrC : std_logic;                     -- Reset $Stage1WrPtr
signal IncStage1WrC : std_logic;                     -- Increment $Stage1WrPtr
signal Stage1RdPtr  : unsigned(4 downto 0);          -- 5-Bit Lesezeiger
signal ResStage1RdC : std_logic;                     -- Reset $Stage1RdPtr
signal IncStage1RdC : std_logic;                     -- Increment $Stage1RdPtr
signal Stage1WordsR : unsigned(4 downto 0);          -- 5-Bit Füllstandszähler
signal ResSt1WrdC   : std_logic;                     -- Reset $Stage1WordsR
signal IncSt1WrdC   : std_logic;                     -- Increment $Stage1WordsR
signal DecSt1WrdC   : std_logic;                     -- Decrement $Stage1WordsR

-- RAM-Adresse
signal RamAAddrR    : std_logic_vector(8 downto 0); -- 16-Bit RAM-Adresse (anpassbar)